Field of the Invention
The invention is related to a display apparatus and more particularly, to a source driver apparatus and an operating method thereof.
Description of Related Art
FIG. 1 is a schematic circuit block diagram illustrating a thin film transistor (TFT) liquid crystal display (LCD) 10. The LCD 10 includes a timing controller 11, one or more gate drivers (e.g., gate drivers 12_1 and 12_2 depicted in FIG. 1), one or more source drivers (e.g., source drivers 13_1, 13_2 and 13_3 depicted in FIG. 1) and a display panel 14.
The gate drivers 12_1 and 12_2 are coupled between the timing controller 11 and the display panel 14. After the gate drivers 12_1 and 12_2 receive a vertical start signal STV provided by the timing controller 11, the vertical start signal STV starts to be shifted gradually within the gate drivers 12_1 and 12_2 one by one according to a timing of a gate clock signal CPV. Thus, the gate drivers 12_1 and 12_2 alternately drive each gate line of the display panel 14 one by one according to the shifting positions of the vertical start signal STV. For instance, a gate line GD1 is first driven, then gate lines GD2 and GD3 are driven and so on. The timing controller 11 provides an output enable signal OE (or a disable signal) the gate drivers 12_1 and 12_2 through a control bus to control pulse widths of gate driving signals output by the gate drivers 12_1 and 12_2.
The source drivers 13_1, 13_2 and 13_3 are coupled between the timing controller 11 and the display panel 14. After the source drivers 13_1, 13_2 and 13_3 receive a horizontal start signal STH provided by the timing controller 11, the horizontal start signal STH is shifted gradually among the source drivers 13_1, 13_2 and 13_3 according to a timing of a source clock signal CK. The timing controller 11 outputs a plurality of line data (i.e., display data) in a string form to the data line bus DAT. Thus, the source drivers 13_1, 13_2 and 13_3 may obtain the display data from the data line bus DAT. The data line bus DAT is, for example, a bus complying with the mini low voltage differential signaling (mini-LVDS) standard. Based on the control of the source clock signal CK and the horizontal start signal STH output by the timing controller 11, the source drivers 13_1, 13_2 and 13_3 may latch different display data from the data line bus DAT in corresponding driving channels. Based on the control of a line latch signal LD, the source drivers 13_1, 13_2 and 13_3 may simultaneously convert the display data latched in the driving channels into source driving signals. According to a scanning timing of the gate drivers 12_1 and 12_2, the source driving signals may be written into a plurality of pixel units (e.g., pixel units P1, P2, P3, P4, P5, P6, P7, P8 and P9 depicted in FIG. 1) of the display panel 14 to display an image.
The display panel 14 is formed by two substrates, and a liquid crystal material (i.e., a LCD layer) is filled between the two substrates. The display panel 14 is configured with a plurality of source lines (or referred to as data lines, e.g., source lines SD1, SD2 and SD3 depicted in FIG. 1), a plurality of gate lines (or referred to as scan lines, e.g., the gate lines GD1, GD2 and GD3 depicted in FIG. 1) and a plurality of pixel units (e.g., the pixel units P1, P2, P3, P4, P5, P6, P7, P8 and P9 depicted in FIG. 1). The source lines SD1, SD2 and SD3 are vertical to the gate lines GD1, GD2 and GD3. The pixel units P1 through P9 are arranged in an array on the display panel 14. FIG. 1 illustrates an exemplary example of a circuit diagram of the pixel unit P3, and the other pixel units P1 through P2, P4 through P9 may be derived with reference to the circuit diagram of the pixel unit P3.
The gate drivers 12_1 and 12_2 outputs the gate driving signals to the gate lines GD1, GD2 and GD3. The gate driving signals cause transmission delay due to RC loads on the gate lines. FIG. 1 illustrates equivalent circuits of the gate lines GD1, GD2 and GD3, where resistor symbols are used to represent equivalent resistors (or parasitic resistors) on the gate lines, while capacitor symbols are used to represent equivalent capacitors (or parasitic capacitors) on the gate lines. The parasitic resistors and the parasitic capacitors gate lines form the RC loads which cause delay to signal transmission. As the size of the display panel 14 is increased, the delay effect of the gate lines become obvious, and a position with the maximum distance to the gate driver has the most serious delay effect.
FIG. 2 is a timing diagram illustrating the signals depicted in FIG. 1. With reference to FIG. 1 and FIG. 2, a pulse of the gate line GD2 starts to rise up after a pulse of the gate line GD1 ends. The RC load of the gate line GD1 causes the transmission delay, such that the gate driving signals GD1a, GD1b and GD1c received by the pixel units P1, P2 and P3 have different delay times. The gate driving signals GD1a, GD1b and GD1c and the delay times correspond to distances from the pixel units P1, P2 and the P3 to the gate driver 12_1. Similarly, the RC load of the gate line GD2 causes the transmission delay, such that the gate driving signals GD2a, GD2b and GD2c received by the pixel units P4, P5 and P6 have different delay times. The gate driving signals GD2a, GD2b and GD2c and the delay times correspond to distances from the pixel units P4, P5 and P6 to the gate driver apparatus 12_1.
In order to ensure all the pixel units of the previous gate line (e.g., the gate line GD1) are turned off) for the pixel units of the next gate line (e.g., the gate line GD2) to be turned on, the timing controller 11 may use an enable signal OE to narrow the pulse widths of the gate driving signals. Narrowing the pulse widths of the gate driving signals means shortening a charging time of a source driver charging the pixel units. However, a shortened charging time would lead to display abnormality due to the pixel units being insufficiently charged. This issue becomes worse in panels with larger sizes.
According to FIG. 2, for the same gate line GD2, the pixel unit P4 closer to the gate driver apparatus 12_1 obtains a greater effective charging time Tch1. An effective charging time Tch2 of the pixel unit P5 departing away from the gate driver apparatus 12_1 is smaller than the effective charging time Tch1 of the pixel unit P4, and an effective charging time Tch3 of the pixel unit P6 departing away from the gate driver apparatus 12_1 is further smaller than the effective charging time Tch2 of the pixel unit P5. As the effective charging time is shortened, the pixel units (e.g., the pixel unit P6 and/or pixel unit P5) departing away from the gate driver apparatus 12_1 would cause display abnormality due to the pixel units being insufficiently charged.